Output Router and Adder¶

The Output Router and Adder is a software upgrade option for the SHFQC+. The option can be installed in the field.

Features¶

Signals from up to three additional Digital Signal Units can be routed and added to any Output of an SG Channel
Independent amplitude and phase control for each routed signal
Ability to enable each routed signal separately
Overflow counter to indicate if the added signals saturate the DAC
Gain access to additional Digital Signal Units for extended signal generation capabilities on some instruments

Description¶

The Output Router and Adder is a feature that allows the user to flexibly route the signals generated by different Digital Signal Units to any front panel Output of an SG Channel. The same signal can be routed to multiple Outputs at once, and the user has completely independent amplitude and phase control of each routed instance of a signal. This can have uses in crosstalk compensation on the RF lines for superconducting qubits, but it can also be used to simultaneously drive multiple hyperfine transitions in color centers, to perform state transfer protocols in quantum optics, or to perform other experiments where frequency multiplexing is needed.

The Output Router and Adder works by introducing additional signal line connections between the different digital signal pathways that lead to the analog upconversion chains of the Outputs. The functional diagram below highlights how a signal could be routed from the Digital Signal Unit of SG Channel 2 to the Output of SG Channel 1.

Figure 1: Diagram showing how the digital signals are routed between SGChannels. The default signal pathways are shown in black, whereas the additional pathways and controls are highlighted in light blue.

In this case, the digital signal generated by AWG 2 and modulated by the Digital Modulation settings of SG Channel 2 is routed to the digital signal line that leads to the analog upconversion chain of SG Channel Output 1, with the routed signal indicated by the light blue connections leading from SG Channel 2 to SG Channel 1. The user has the ability to add an additional amplitude scaling factor and phase shift to the routed signal, indicated by \(A_{11}\) and \(\phi_{11}\) in the diagram. The signal that is generated at SG Channel Output 1 will therefore be a linear combination of the signal normally generated from AWG core 1, as well as an amplitude-scaled and phase-shifted version of the signal generated by AWG core 2 and Digital Modulation settings of SGChannel 2. For detailed information on how the signals from the Digital Signal Units are generated and how the Digital Modulation settings are applied, please refer to the Digital Modulation Tutorial. Similarly, for more information on how the DAC and the Frequency Upconversion Chain convert the digital signals into the final analog signal at the desired RF center frequency, please refer to the In/Out Tab.

Note

It is not possible to route marker or trigger output data between Channels: Only waveform information is routed.

Each SG Channel has three routes, corresponding to the three additional digital signals that can be added to the default signal pathway of that channel. Each route has its own enable/disable switch, source (to select which channel the signal should be drawn from), amplitude scaling factor, and phase shift. All of the signal routing, signal addition, amplitude scaling, and phase shifting happens digitally, before the digital-to-analog conversion and associated analog upconversion chain. The node device.sgchannels[n].outputrouter.overflowcount() can be queried to determine whether the total signal, comprising the default signal for that SG Channel Output as well as all routed signals that are added to it, has produced an overflow at the DAC, indicating that the signal was clipped. If the Output Router and Adder has detected an overflow in the past, it automatically clamps the signal to be within the range [-1, 1], possibly distorting the signal. Both the amplitude scaling factor and the phase shift of each routed signal are floating numbers that are serialized to 16 bits before being written to the FPGA. The table below summarizes each of the different node settings that are part of the Output Router and Adder.

Table 1: Output Router and Adder node settings
Name	Node	Description
Channel n Output Router Enable	`device.sgchannels[n].outputrouter.enable()`	Enables (`1`) or disables (`0`) the Output Router and Adder of Channel n
Channel n Output Router Overflow Indicator	`device.sgchannels[n].outputrouter.overflowcount()`	Indicates the number of overflow events that have occurred
Channel n Route m Enable	`device.sgchannels[n].outputrouter.routes[m].enable()`	Enables (`1`) or disables (`0`) Route m (0-2) of the Output Router and Adder of Channel n
Channel n Route m Source	`device.sgchannels[n].outputrouter.routes[m].source()`	Index of the Channel from which Route m accepts the additional digital signal. Note that it is not possible to use the same Channel index on different Routes on the same Channel at the same time (e.g. it is not possible to have both `device.sgchannels[0].outputrouter.routes[0].source(1)` and `device.sgchannels[0].outputrouter.routes[1].source(1)` simultaneously). Similarly, the Output Router of a Channel does not accept its own index as a Source (e.g. it is not allowed to set `device.sgchannels[n].outputrouter.routes[m].source(n)`)
Channel n Route m Amplitude	`device.sgchannels[n].outputrouter.routes[m].amplitude()`	Amplitude scaling factor (between 0 and 1, serialized into 16 bits) applied to the routed signal. Indicated by \(A_{nm}\) in diagrams and equations.
Channel n Route m Phase	`device.sgchannels[n].outputrouter.routes[m].phase()`	Phase shift (any real value, serialized into 16 bits) applied to the routed signal. Indicated by \(\phi_{nm}\) in diagrams and equations.

Based on the figure and table above, we can write down the total I and Q signals that are present on SG Channel 1. Before reaching the Output Router and Adder, SG Channels 1 and 2 create the following I and Q signals:

\[ V_{I,\mathrm{Ch1}}(t) = \mathrm{Gain00_{\mathrm{Ch1}}} \times w_{I,\mathrm{Ch1}} (t) \cos(2 \pi f_{\mathrm{Osc,\mathrm{Ch1}}} t + \phi_\mathrm{Ch1}) + \mathrm{Gain01_{\mathrm{Ch1}}} \times w_{Q,\mathrm{Ch1}} (t) \sin(2 \pi f_{\mathrm{Osc,\mathrm{Ch1}}} t + \phi_\mathrm{Ch1}) \\ \newline V_{Q,\mathrm{Ch1}}(t) = \mathrm{Gain10_{\mathrm{Ch1}}} \times w_{I,\mathrm{Ch1}} (t) \sin(2 \pi f_{\mathrm{Osc,\mathrm{Ch1}}} t + \phi_\mathrm{Ch1}) + \mathrm{Gain11_{\mathrm{Ch1}}} \times w_{Q,\mathrm{Ch1}} (t) \cos(2 \pi f_{\mathrm{Osc,\mathrm{Ch1}}} t + \phi_\mathrm{Ch1}) \\ \newline V_{I,\mathrm{Ch2}}(t) = \mathrm{Gain00_{\mathrm{Ch2}}} \times w_{I,\mathrm{Ch2}} (t) \cos(2 \pi f_{\mathrm{Osc,\mathrm{Ch2}}} t + \phi_\mathrm{Ch2}) + \mathrm{Gain01_{\mathrm{Ch2}}} \times w_{Q,\mathrm{Ch2}} (t) \sin(2 \pi f_{\mathrm{Osc,\mathrm{Ch2}}} t + \phi_\mathrm{Ch2}) \\ \newline V_{Q,\mathrm{Ch2}}(t) = \mathrm{Gain10_{\mathrm{Ch2}}} \times w_{I,\mathrm{Ch2}} (t) \sin(2 \pi f_{\mathrm{Osc,\mathrm{Ch2}}} t + \phi_\mathrm{Ch2}) + \mathrm{Gain11_{\mathrm{Ch2}}} \times w_{Q,\mathrm{Ch2}} (t) \cos(2 \pi f_{\mathrm{Osc,\mathrm{Ch2}}} t + \phi_\mathrm{Ch2}) \]

where all of the symbols are as defined in the Digital Modulation Tutorial, and the subscript \(\mathrm{Ch}n\) indicates from which SG Channel the signal or setting originates. At this stage, these are digital I and Q signals, not analog voltages, that will be sent to the double-superheterodyne upconversion scheme explained in the In/Out Tab. It is these digitally modulated I and Q signals that are routed between channels. In this case, we are using the default signal of SG Channel 1 as well as the first route of the Output Router and Adder, with SG Channel 2 as the source for that route. The total I and Q signals that are sent to the DAC and Output of SG Channel 1 are therefore given by the following equation:

\[ V_{I,\mathrm{Ch1},\mathrm{Total}}(t) = V_{I,\mathrm{Ch1}}(t) + A_{00} \left( V_{I,\mathrm{Ch2}}(t) \cos(\phi_{00}) - V_{Q,\mathrm{Ch2}}(t) \sin(\phi_{00}) \right) \\ \newline V_{Q,\mathrm{Ch1},\mathrm{Total}}(t) = V_{Q,\mathrm{Ch1}}(t) + A_{00} \left( V_{I,\mathrm{Ch2}}(t) \sin(\phi_{00}) + V_{Q,\mathrm{Ch2}}(t) \cos(\phi_{00}) \right) \]

where \(A_{00}\) and \(\phi_{00}\) stand for the node settings device.sgchannels[0].outputrouter.routes[0].amplitude() and device.sgchannels[0].outputrouter.routes[0].phase(), as described in the table above. Because all of the signal routing and adding happens digitally, all frequency components of the total signal should lie within the 1 GHz bandwidth of the analog upconversion chain, or there is a risk of attenuating parts of the generated RF signal. For use cases in which frequency multiplexing in a bandwidth exceeding 1 GHz is needed, it is recommended to combine the desired RF signals external to the instrument. This also means that all channels between which crosstalk compensation is being performed must share the same RF center frequency, such that the compensation pulse appears at the correct frequency at the Output.

Note that enabling the Output Router on a given channel increases the output latency by 26 ns (52 samples), as the signal pathway is extended to include additional signal addition stages. It is highly recommended to enable the Output Router on all channels that are sharing signals in any way, to ensure that the signals at the SG Outputs on the front panel remain synchronized. For example, if AWG core 2 is generating a signal that is routed to SG Output 1, it is recommended to enable the Output Router on SG Channel 2 as well, even though it is not adding signals from other channels to its own output. This is to ensure that the relative timing of the signal from SG Channel 2 played on SG Channel Output 2 lines up with the SG Channel 2 signal played on SG Output 1.

For instruments that have fewer than the maximum possible number of AWG cores for the instrument class, additional Digital Signal Units become available. This means that an SHFQC2 (SHFQC4) will have access to 6 AWG cores in total, as well as the corresponding Digital Modulation settings and other digital signal settings, such as the digital trigger and the mask, shift, and offset settings for processing data received over DIO or ZSync. The first 2 (4) AWG cores, with indices 0 – 1 (0 – 3), and corresponding Digital Modulation settings come with the SHFQC2 (SHFQC4) by default. The 4 (2) additional Digital Signal Units, with indices 2 – 5 (4 – 5), grant access to both another AWG core and Digital Modulation settings with which to modulate the AWG signals, as well as other several other settings needed to configure the digital signal pathways. The additional Digital Signal Units have all the same settings and abilities as the channels that come with the base version of the instrument, but they are not associated with an SG Channel Output on the front panel by default and therefore do not generate an output signal unless their signals are intentionally routed to an Output using the Output Router and Adder. The table below lists the functionality that is NOT available on the additional Digital Signal Units.

Table 2: Node settings that are NOT available on the additional Digital Signal Units made available with the Output Router and Adder
Name	Node
Channel n Digitalmixer Center Frequency	`device.sgchannels[n].digitalmixer.centerfreq()`
Channel n Marker Source	`device.sgchannels[n].marker.source()`
Channel n Output Center Frequency	`device.sgchannels[n].centerfreq()`
Channel n Output Delay	`device.sgchannels[n].output.delay()`
Channel n Output Filter	`device.sgchannels[n].output.filter()`
Channel n Output On	`device.sgchannels[n].output.on()`
Channel n Output Over Range Counter	`device.sgchannels[n].output.overrangecount()`
Channel n Output Range	`device.sgchannels[n].output.range()`
Channel n Output RFLF Path	`device.sgchannels[n].output.rflfpath()`
Channel n Synthesizer	`device.sgchannels[n].synthesizer()`
Channel n Trigger Delay	`device.sgchannels[n].trigger.delay()`
Channel n Trigger Impedance (50 Ohm)	`device.sgchannels[n].trigger.imp50()`
Channel n Trigger Level	`device.sgchannels[n].trigger.level()`
Channel n Trigger Value	`device.sgchannels[n].trigger.value()`

All of the above settings involve analog settings or other settings involved in the upconversion chain that do not apply to the additional Digital Signal Units. Although the node device.sgchannels[n].output.delay() is a digital delay, its effects are applied after the Output Router and Adder but before the DAC and is therefore not needed for the additional Digital Signal Units. Having the delay node implemented after the Output Router and Adder also ensures that the delay on a given Output is common to all signals applied on that line.

How-To: Route signals between Channels 1, 2, 4, and 6¶

For motivation, consider a superconducting qubit chip in which SG Channels 1 – 6 (e.g. of an SHFQC6 ) are connected to Qubits 1 – 6 and in which Qubit 4 experiences strong crosstalk to Qubits 1, 2, and 6. Assuming the amplitude of the crosstalk has been characterized, as has the necessary phase shift for the compensation pulse, we can use the following node settings to enable the instrument to automatically play compensation pulses, such that the net effect of the crosstalk at the qubit is negated.

We assume that the instrument has already been connected to and that all of the AWGs and Digital Modulation settings have been programmed or set up.

# Define paths for Output Routers of each channel used
ch1_rtr = device.sgchannels[0].outputrouter
ch2_rtr = device.sgchannels[1].outputrouter
ch4_rtr = device.sgchannels[3].outputrouter
ch6_rtr = device.sgchannels[5].outputrouter

with sg.set_transaction():
  ## Signals routed to Output 1
  ch1_rtr.enable(1) # allow other signals to be added to the output of this channel
  ch1_rtr.routes[0].enable(1) # enable route 1
  ch1_rtr.routes[0].source(3) # for route 1, use SG channel 4 as the source
  ch1_rtr.routes[0].amplitude(AMP_Q4_TO_Q1) # apply an amplitude scaling factor of AMP_Q4_TO_Q1, corresponding to the amount of leakage from charge line 4 into qubit 1
  ch1_rtr.routes[0].phase(PHASE_Q4_TO_Q1) # apply a phase shift of PHASE_Q4_TO_Q1 degrees to the routed signal, corresponding to the phase shift needed to cancel out the leakage from charge line 4 into qubit 1

  ## Signals routed to Output 2
  ch2_rtr.enable(1) # allow other signals to be added to the output of this channel
  ch2_rtr.routes[0].enable(1) # enable route 1
  ch2_rtr.routes[0].source(3) # for route 1, use SG channel 4 as the source
  ch2_rtr.routes[0].amplitude(AMP_Q4_TO_Q2) # apply an amplitude scaling factor of AMP_Q4_TO_Q6 to the routed signal
  ch2_rtr.routes[0].phase(PHASE_Q4_TO_Q2) # apply a phase shift of PHASE_Q4_TO_Q2

  ## Signals routed to Output 4
  ch4_rtr.enable(1) # allow other signals to be added to the output of this channel
  # Route 1
  ch4_rtr.routes[0].enable(1) # enable route 1
  ch4_rtr.routes[0].source(0) # for route 1, use SG channel 1 as the source
  ch4_rtr.routes[0].amplitude(AMP_Q1_TO_Q4) # apply an amplitude scaling factor of AMP_Q1_TO_Q4 to the routed signal
  ch4_rtr.routes[0].phase(PHASE_Q1_TO_Q4) # apply a phase shift of PHASE_Q1_TO_Q4

  # Route 2
  ch4_rtr.routes[1].enable(1) # enable route 2
  ch4_rtr.routes[1].source(1) # for route 2, use SG channel 2 as the source
  ch4_rtr.routes[1].amplitude(AMP_Q2_TO_Q4) # apply an amplitude scaling factor of AMP_Q2_TO_Q4 to the routed signal
  ch4_rtr.routes[0].phase(PHASE_Q2_TO_Q4) # apply a phase shift of PHASE_Q2_TO_Q4

  # Route 3
  ch4_rtr.routes[2].enable(1) # enable route 1
  ch4_rtr.routes[2].source(5) # for route 3, use SG channel 6 as the source
  ch4_rtr.routes[2].amplitude(AMP_Q6_TO_Q4) # apply an amplitude scaling factor of AMP_Q6_TO_Q4 to the routed signal
  ch4_rtr.routes[2].phase(PHASE_Q6_TO_Q4) # apply a phase shift of PHASE_Q6_TO_Q4

  ## Signals routed to Output 6
  ch6_rtr.enable(1) # allow other signals to be added to the output of this channel
  ch6_rtr.routes[0].enable(1) # enable route 1
  ch6_rtr.routes[0].source(3) # for route 1, use SG channel 4 as the source
  ch6_rtr.routes[0].amplitude(AMP_Q4_TO_Q6) # apply an amplitude scaling factor of AMP_Q4_TO_Q6 to the routed signal
  ch6_rtr.routes[0].phase(PHASE_Q4_TO_Q6) # apply a phase shift of PHASE_Q4_TO_Q6 degrees to the routed signal

With these settings, any sequence played on SG Channel 4 will automatically play compensation pulses on SG Channel Outputs 1, 2, and 6. Similarly, any sequence played on SG Channels 1, 2, or 6 will automatically play a compensation pulse on SG Channel Output 4 (so long as the corresponding AWG cores and analog Outputs are all enabled).

Since we are adding many signals together on SG Channel Output 4, there is a risk that the total signal could saturate the DAC at some points. To check whether this is the case, a user can query the node device.sgchannels[3].outputrouter.overflowcount(). The result is the number of overflows that have occurred so far, and a non-zero result means that an overflow has occurred in the past, and the digital signals must be scaled down. This can be accomplished, for example, by increasing the range setting of the SG Channel Output and reducing the digital amplitudes of all signals to compensate. A result of 0 means that no overflow has occurred.