Specifications

Important

Unless otherwise stated, all specifications apply after 30 minutes of instrument warm-up.

For measurements in which high gate fidelity is crucial, it is highly recommended to enable all required outputs and inputs and wait for 2 hours after powering on the instrument.

Important

Important changes in the specification parameters are explicitly mentioned in the revision history of this document.

General Specifications

Table 1: General and storage

Parameter	Min	Typ	Max
storage temperature	–25 °C	-	65 °C
storage relative humidity (non-condensing)	-	-	95%
operating temperature	5 °C	-	40 °C
operating relative humidity (non-condensing)	-	-	90%
specification temperature	18 °C	-	28 °C
power consumption	-	-	300 W
operating environment	IEC61010, indoor location, installation category II, pollution degree 2
operating altitude	up to 2000 meters
power inlet fuses	250 V, 2 A, fast acting, 5 x 20 mm
power supply AC line	100-240 V (±10%), 50/60 Hz
dimensions (width x depth x height)	45.0 × 39.7 × 13.2 cm (no handle), 17.7 × 15.6 × 5.2 inch, 19 inch rack compatible
weight	15 kg (33 lb)
recommended calibration interval	2 years

Table 2: Maximum ratings

Parameter	Min	Typ	Max
damage threshold Out	-	-	+30 dBm
damage threshold In	-	-	+20 dBm
damage threshold Mark Out	–0.7 V	-	+4 V
damage threshold Trig In (1 kΩ input impedance)	–11 V	-	+11 V
damage threshold Trig In (50 Ω input impedance)	–6 V	-	+6 V
damage threshold Aux In (DC)	-10 V	-	+10 V
damage threshold Aux In (AC)	-	-	+20 dBm
damage threshold External Clk In (DC)	–3 V	-	+3 V
damage threshold External Clk In (AC, with DC offset 0 V)	-	-	+13.5 dBm
damage threshold External Clk Out (DC)	–3 V	-	+3 V
MDS In / Out	–0.7 V	-	+4 V
DIO In / Out in default configuration 3.3 V CMOS/TTL	–0.7 V	-	+4 V
torque limit front panel SMA connectors	-	-	0.5 Nm
torque limit back panel SMA connectors	-	-	1.0 Nm

Table 3: Host computer requirements

Parameter	Description
supported Windows operating systems	Windows 10, 8.1, 7 on x86-64
supported macOS operating systems	macOS 10.11+ on x86-64 and ARMv8
supported Linux distributions	GNU/Linux (Ubuntu 14.04+, CentOS 7+, Debian 8+) on x86-64 and ARMv8
minimum host computer requirements a	Windows 7 64-bit Dual Core CPU 4 GB DRAM 1 Gbit/s Ethernet controller
recommended host computer requirements a	Windows 10 or GNU/Linux or macOS Quad Core CPU (i7) or better 8 GB DRAM or better 1 Gbit/s Ethernet controller USB 3.0 connection
supported processors	x86-64 (Intel, AMD), ARMv8 (e.g., Raspberry Pi 4, Apple M1)

Analog Interface Specifications

Table 4: Signal Outputs

Parameter	Details		Min	Typ	Max
connectors	-		SMA, front panel single-ended
output impedance	-		-	50 Ω	-
output coupling	-		AC
synthesizer frequency range	synthesizer shared with Signal Input of the same Channel		1-8 GHz
instantaneous bandwidth (–3dB)	RF path		±500 MHz
	LF path		DC - 800 MHz
total output frequency range	RF path		0.5 GHz	-	8.5 GHz
	LF path		DC	-	800 MHz
output range	RF path, into 50 Ω		-30 dBm	-	+10 dBm
	LF path, into 50 Ω		-30 dBm	-	+5 dBm
output level temperature drift	direct		-	0.15 dB/C	-
	when looped with Signal Input		-	0.25 dB/C	-
D/A converter vertical resolution	-		14 bit
D/A converter sampling rate	after internal x3 interpolation		6 GSa/s
output phase noise	10 dBm, 1 GHz	offset 0.1 kHz	-	-83 dB/Hz	-
		offset 1 kHz	-	-92 dBc/Hz	-
		offset 10 kHz	-	-100 dBc/Hz	-
		offset 100 kHz	-	-102 dBc/Hz	-
	10 dBm, 4 GHz	offset 0.1 kHz	-	-82 dBc/Hz	-
		offset 1 kHz	-	-91 dBc/Hz	-
		offset 10 kHz	-	-100 dBc/Hz	-
		offset 100 kHz	-	-101 dBc/Hz	-
	10 dBm, 6 GHz	offset 0.1 kHz	-	-81 dBc/Hz	-
		offset 1 kHz	-	-90 dBc/Hz	-
		offset 10 kHz	-	-98 dBc/Hz	-
		offset 100 kHz	-	-100 dBc/Hz	-
	10 dBm, 8 GHz	offset 0.1 kHz	-	-80 dBc/Hz	-
		offset 1 kHz	-	-88 dBc/Hz	-
		offset 10 kHz	-	-96 dBc/Hz	-
		offset 100 kHz	-	-98 dBc/Hz	-
output spurious free dynamic range (excluding harmonics)	0 dBm, 1 GHz	-800 to 800 MHz	-	74 dBc	-
	0 dBm, 4 GHz		-	66 dBc	-
	0 dBm, 6 GHz		-	60 dBc	-
	0 dBm, 8 GHz		-	65 dBc	-
output worst harmonic component	10 dBm, 1 GHz	-800 to 800 MHz	-	-40 dBc	-
	10 dBm, 4 GHz		-	-40 dBc	-
	10 dBm, 6 GHz		-	-38 dBc	-
	10 dBm, 8 GHz		-	-36 dBc	-

Table 5: Time Domain Output Characteristics

Parameter	Details	Min	Typ	Max
skew adjustment resolution	-	-	2 ns	-

Table 6: Signal Inputs

Parameter	Details		Min	Typ	Max
connectors	-		SMA, front panel single-ended
input impedance	-		-	50 Ω	-
input coupling	-		AC
synthesizer frequency range	synthesizer shared with Signal Output of the same Channel		1-8 GHz
instantaneous bandwidth (–3dB)	RF path		±500 MHz
	LF path		DC - 800 MHz
total input frequency range	RF path		0.5 - 8.5 GHz
	LF path		DC - 800 MHz
input range	RF path, into 50 Ω		-50 dBm	-	+10 dBm
	LF path, into 50 Ω		-30 dBm	-	+10 dBm
input level accuracy at carrier frequency and 23°C	≤1 Vpp and <4 GHz		-	± 0.5 dB	-
	≤1 Vpp and <8 GHz		-	± 1 dB	-
	>8 GHz		-	± 3 dB	-
input level temperature drift	direct		-	0.15 dB/C	-
	when looped with Signal Output		-	0.25 dB/C	-
A/D converter vertical resolution	-		14 bit
A/D converter sampling rate	before internal x2 decimation		4 GSa/s
input voltage noise density	10 dBm, 1 GHz	in-band noise measured with room-temperature 50 Ω cap	-	-130 dBm/Hz (71 nV/√Hz)	-
	0 dBm, 1 GHz		-	-134 dBm/Hz (45 nV/√Hz)	-
	-10 dBm, 1 GHz		-	-145 dBm/Hz (13 nV/√Hz)	-
	-20 dBm, 1 GHz		-	-142 dBm/Hz (18 nV/√Hz)	-
	-30 dBm, 1 GHz		-	-162 dBm/Hz (1.78 nV/√Hz)	-
	-40 dBm, 1 GHz		-	-165 dBm/Hz (1.26 nV/√Hz)	-
	-50 dBm, 1 GHz		-	-166 dBm/Hz (1.12 nV/√Hz)	-
input spurious free dynamic range (excluding harmonics)	10 dBm	signal at center frequency, max. amplitude, -750 to 750 MHz	-	54 dBc	-
	0 dBm		-	54 dBc	-
	-10 dBm		-	55 dBc	-
	-20 dBm		-	50 dBc	-
	-30 dBm		-	58 dBc	-
	-40 dBm		-	53 dBc	-
	-50 dBm		-	45 dBc	-
3rd order intermodulation distortion	10 dBm	dual tone with -7 dBFS of range with 150 MHz Splitting from 1 GHz to 8 GHz	-	45 dBc	-
	0 dBm		-	54 dBc	-
	-10 dBm		-	54 dBc	-
	-20 dBm		-	56 dBc	-
	-30 dBm		-	54 dBc	-
	-40 dBm		-	50 dBc	-
	-50 dBm		-	40 dBc	-

Table 7: Marker Outputs & Trigger Inputs

Parameter	Details	Min	Typ	Max
marker outputs	-	2 per channel, SMA output on front panel
marker output high voltage	-	-	3.3 V	-
marker output low voltage	-	-	0 V	-
marker output impedance	-	-	50 Ω	-
marker output rise time 20% to 80%	-	-	300 ps	-
marker output period jitter	square wave, 100 MHz	-	60 ps p-p	-
trigger inputs	-	2 per channel, 2 SMA on front panel
trigger input impedance	-	50 Ω / 1 kΩ
trigger input voltage range	50 Ω impedance	–5 V	-	5 V
		1 kΩ impedance	–10 V	-	10 V
trigger input threshold range	50 Ω impedance	–5 V	-	5 V
		1 kΩ impedance	–10 V	-	10 V
trigger input threshold resolution	-	-	< 0.4 mV	-
trigger input threshold hysteresis	-	-	> 60 mV	-
trigger input min. pulse width	-	-	5 ns	-
trigger input max. operating frequency	-	-	300 MHz	-

Table 8: Other Inputs and Outputs

Parameter	Details	min	Typ	Max
reference clock input	-	SMA on back panel
reference clock input impedance	-	50 Ω, AC coupled
reference clock input frequency	-	10 / 100 MHz
reference clock input amplitude	10 MHz	-4 dBm	-	+13 dBm
		100 MHz	–5 dBm	-	+13 dBm
reference clock output	-	SMA on back panel
reference clock output impedance		50 Ω, AC coupled
reference clock output amplitude	into 50 Ω	2 Vpp	-	5 Vpp
reference clock output frequency		10/100 MHz
reference clock output jitter	derived from integrated phase noise measurement (12 kHz to 20 MHz offset frequency)	-	280 fs RMS	-

Table 9: Oscillator and Clocks

Parameter	Details	Min	Typ	Max
internal clock type	-	OCXO
internal clock long term accuracy / aging	-	-	-	±0.3 ppm/year
internal clock short term stability (1 s)	-	-	-	±0.05 ppm
internal clock initial accuracy	-	-	-	±0.5 ppm
internal clock temperature stability	–20°C to 70°C	-	-	±0.5 ppm
internal clock phase noise	offset 100 Hz	-	–135 dBc/Hz	-
		offset 1 kHz	-	–157 dBc/Hz	-

Digital Signal Processing Specifications

Table 10: Readout Pulse Generator

Parameter	Details	Specification
number of readout pulse generators	-	1 per channel
waveform memory per channel	for SHFQA 2-channel base version	32 kSa total memory, 8 memory blocks with 4 kSa for arbitrary waveform storage, freely configurable and triggerable
		for SHFQA 2-channel + SHFQA-16W	64 kSa total memory, 16 memory blocks with 4 kSa for arbitrary waveform storage, freely configurable and triggerable
		for SHFQA 4-channel	64 kSa total memory, 16 memory blocks with 4 kSa for arbitrary waveform storage, freely configurable and triggerable
sequence length	-	16,384
waveform granularity	-	4 samples
minimum waveform length	-	4 samples
sequencer clock frequency	-	250 MHz

Table 11: Qubit Measurement Unit

Parameter	Details	Specification
number of Qubit Measurement Units	-	1 per channel
number of integration weights per Qubit Measurement Unit (total for full instrument)	for SHFQA 2-channel base version	8 (16 total)
		for SHFQA 2-channel + SHFQA-16W	16 (32 total)
		for SHFQA 4-channel	16 (64 total)
integration weight time resolution	-	0.5 ns
integration weight length	-	4 kSa
minimum weight length	-	4 samples
integration weight granularity	-	4 samples
multistate discrimination	-	yes
number of distinguishable states	-	up to 4

Table 12: Monitor scope and Trigger Engine

Parameter	Details	Specification
monitor scope (shared between all readout channels)	memory	1 channel: 2^18 2 channels: 2^17 3 & 4 channels: 2^16
		max. averages	2^16

Digital Interface Specifications

Table 13: Digital Interfaces

Parameter	Description
host computer connection	USB 3.0, 1.6 Gbit/s (1 communication, 1 maintenance)
		1GbE, LAN / Ethernet, 1 Gbit/s
DIO port	4 x 8 bit, general purpose digital input/output port, 3.3 V TTL specification
ZSync peripheral port	connector for ZI proprietary bus to communicate with external peripherals (2 times)

DIO Port

The DIO port is a VHDCI 68 pin connector as introduced by the SPI-3 document of the SCSI-3 specification. It is a female connector that requires a 32 mm wide male connector. The interface standard is switchable between LVDS (low-voltage differential signalling) and LVCMOS/LVTTL. The DIO port features 32 user-controlled bits that can all be configured byte-wise as inputs or outputs in LVCMOS/LVTTL mode, whereas in LVDS mode, half of the bits are always configured as inputs. For more specifics on how the user-definable pins can be set.

Figure 1: DIO HD 68 pin connector

Table 14: Electrical Specifications

Parameter	Details	Min	Typ	Max
supported DIO interface standards	-	LVCMOS/LVTTL (single-ended, 3.3 V); LVDS (differential)
high-level input voltage VIH	LVCMOS/LVTTL	2.0 V	-	-
low-level input voltage VIL	LVCMOS/LVTTL	-	-	0.8 V
high-level output voltage VOH	LVCMOS/LVTTL at IOH < 12 mA	2.6 V	-	-
low-level output voltage VOL	LVCMOS/LVTTL at IOL < 12 mA	-	-	0.4 V
high-level output current IOH (sourcing)	LVCMOS/LVTTL	-	-	12 mA
low-level output current IOL (sinking)	LVCMOS/LVTTL	-	-	12 mA
input differential voltage VID	LVDS	100 mV	-	600 mV
input common-mode voltage VICM	LVDS	0.3 V	-	2.35 V
output differential voltage VOD	LVDS	247 mV	-	454 mV
output common-mode voltage VOCM	LVDS	1.125 V	-	1.375 V

Table 15: DIO Pin Assignment in LVCMOS/LVTTL Mode

Pin	Name	Description
68	CLKI	digital input
67	unused	leave unconnected
66 .. 59	DIO[31:24]	digital input or output byte (set by user)
58 .. 51	DIO[23:16]	digital input or output byte (set by user)
50 .. 43	DIO[15:8]	digital input or output byte (set by user)
42 .. 35	DIO[7:0]	digital input or output byte (set by user)
34	GND	digital ground
33	unused	leave unconnected
32 .. 1	GND	digital ground

Table 16: DIO Pin Assignment in LVDS Mode

Pin	Name	Description
68	CLKI+	digital input
67	unused	leave unconnected
66 .. 59	DI+[31:24]	digital input byte
58 .. 51	DI+[23:16]	digital input byte
50 .. 43	DIO+[15:8]	digital input or output byte (set by user)
42 .. 35	DIO+[7:0]	digital input or output byte (set by user)
34	CLKI–	digital input
33	unused	leave unconnected
32 .. 25	DI–[31:24]	digital input byte
24 .. 17	DI–[23:16]	digital input byte
16 .. 9	DIO–[15:8]	digital input or output byte (set by user)
8 .. 1	DIO–[7:0]	digital input or output byte (set by user)