Specifications

storage temperature

–25 °C

-

65 °C

storage relative humidity (non-condensing)

-

-

95%

operating temperature

5 °C

-

40 °C

operating relative humidity (non-condensing)

-

-

90%

specification temperature

18 °C

-

28 °C

power consumption

-

-

300 W

operating environment

IEC61010, indoor location, installation category II, pollution degree 2

operating altitude

up to 2000 meters

power inlet fuses

250 V, 2 A, fast acting, 5 x 20 mm

power supply AC line

100-240 V (±10%), 50/60 Hz

dimensions (width x depth x height)

45.0 × 39.7 × 13.2 cm (no handle), 17.7 × 15.6 × 5.2 inch, 19 inch rack compatible

weight

15 kg (33 lb)

recommended calibration interval

2 years

damage threshold Out

-

-

+30 dBm

damage threshold Mark Out

–0.7 V

-

+4 V

damage threshold Trig In (1 kΩ input impedance)

–11 V

-

+11 V

damage threshold Trig In (50 Ω input impedance)

–6 V

-

+6 V

damage threshold Aux In (DC)

-10 V

-

+10 V

damage threshold Aux In (AC)

-

-

+20 dBm

damage threshold External Clk In (DC)

–3 V

-

+3 V

damage threshold External Clk In (AC, with DC offset 0 V)

-

-

+13.5 dBm

damage threshold External Clk Out (DC)

–3 V

-

+3 V

MDS In / Out

–0.7 V

-

+4 V

DIO In / Out in default configuration 3.3 V CMOS/TTL

–0.7 V

-

+4 V

torque limit front panel SMA connectors

-

-

0.5 Nm

torque limit back panel SMA connectors

-

-

1.0 Nm

supported Windows versions

Windows 10 (x86-64)

supported macOS versions

macOS 10.11+ (x86-64)

supported GNU/Linux distributions

Ubuntu 16.04+ (x86-64)

minimum host computer requirements

recommended host computer requirements

supported processors

all 64-bit Intel and AMD processors

connectors

-

SMA, front panel single-ended

output impedance

-

-

50 Ω

-

output coupling

-

AC

synthesizer frequency range

1 synthesizer/channel in SHFSG4, 1 synthesizer/channel pair in SHFSG8

0.6-8 GHz

output range

into 50 Ω

-30 dBm

-

+10 dBm

output level accuracy

into 50 Ω

-

±(1 dBm of setting)

-

output level temperature drift

-

-

0.15 dB/C

-

D/A converter vertical resolution

-

14 bit

D/A converter sampling rate

after internal x3 interpolation

6 GSa/s

output phase noise

10 dBm, 1 GHz

offset 0.1 kHz

-

-83 dB/Hz

-

offset 1 kHz

-

-92 dBc/Hz

-

offset 10 kHz

-

-100 dBc/Hz

-

offset 100 kHz

-

-102 dBc/Hz

-

10 dBm, 4 GHz

offset 0.1 kHz

-

-82 dBc/Hz

-

offset 1 kHz

-

-91 dBc/Hz

-

offset 10 kHz

-

-100 dBc/Hz

-

offset 100 kHz

-

-101 dBc/Hz

-

10 dBm, 6 GHz

offset 0.1 kHz

-

-81 dBc/Hz

-

offset 1 kHz

-

-90 dBc/Hz

-

offset 10 kHz

-

-98 dBc/Hz

-

offset 100 kHz

-

-100 dBc/Hz

-

10 dBm, 8 GHz

offset 0.1 kHz

-

-80 dBc/Hz

-

offset 1 kHz

-

-88 dBc/Hz

-

offset 10 kHz

-

-96 dBc/Hz

-

offset 100 kHz

-

-98 dBc/Hz

-

output spurious free dynamic range (excluding harmonics)

0 dBm, 1 GHz

-800 to 800 MHz

-

74 dBc

-

0 dBm, 4 GHz

-

66 dBc

-

0 dBm, 6 GHz

-

60 dBc

-

0 dBm, 8 GHz

-

65 dBc

-

output worst harmonic component

10 dBm, 1 GHz

-800 to 800 MHz

-

-40 dBc

-

10 dBm, 4 GHz

-

-40 dBc

-

10 dBm, 6 GHz

-

-38 dBc

-

10 dBm, 8 GHz

-

-36 dBc

-

skew adjustment resolution

1 sample clock period

-

<0.5 ns

-

marker outputs

-

1 per channel, SMA output on front panel

marker output high voltage

-

-

3.3 V

-

marker output low voltage

-

-

0 V

-

marker output impedance

-

-

50 Ω

-

marker output rise time 20% to 80%

-

-

300 ps

-

marker output period jitter

square wave, 100 MHz

-

60 ps p-p

-

trigger inputs

-

1 per channel, 1 SMA on front panel

trigger input impedance

-

50 Ω / 1 kΩ

trigger input voltage range

50 Ω impedance

–5 V

-

5 V

1 kΩ impedance

–10 V

-

10 V

trigger input threshold range

50 Ω impedance

–5 V

-

5 V

1 kΩ impedance

–10 V

-

10 V

trigger input threshold resolution

-

-

< 0.4 mV

-

trigger input threshold hysteresis

-

-

> 60 mV

-

trigger input min. pulse width

-

-

5 ns

-

trigger input max. operating frequency

-

-

300 MHz

-

reference clock input

-

SMA on back panel

reference clock input impedance

-

50 Ω, AC coupled

reference clock input frequency

-

10 / 100 MHz

reference clock input amplitude

10 MHz

-4 dBm

-

+13 dBm

100 MHz

–5 dBm

-

+13 dBm

reference clock output

-

SMA on back panel

reference clock output impedance

50 Ω, AC coupled

reference clock output amplitude

into 50 Ω

2 Vpp

-

5 Vpp

reference clock output frequency

10/100 MHz

reference clock output jitter

derived from integrated phase noise measurement (12 kHz to 20 MHz offset frequency)

-

280 fs RMS

-

internal clock type

-

OCXO

internal clock long term accuracy / aging

-

-

-

±0.3 ppm/year

internal clock short term stability (1 s)

-

-

-

±0.05 ppm

internal clock initial accuracy

-

-

-

±0.5 ppm

internal clock temperature stability

–20°C to 70°C

-

-

±0.5 ppm

internal clock phase noise

offset 100 Hz

-

–135 dBc/Hz

offset 1 kHz

-

–157 dBc/Hz

-

Parameter

Details

Specification

number of AWG cores

-

1 per channel

AWG sampling rate

dual-channel

2 GSa/s

waveform memory per output channel

-

98 kSa

sequence length

-

32768 instructions per core

waveform granularity

-

16 samples

minimum waveform length

-

16 samples (with command table)

sequencer clock frequency

-

250 MHz

host computer connection

USB 3.0, 1.6 Gbit/s (1 communication, 1 maintenance)

1GbE, LAN / Ethernet, 1 Gbit/s

DIO port

4 x 8 bit, general purpose digital input/output port, 3.3 V TTL specification

ZSync peripheral port

connector for ZI proprietary bus to communicate with external peripherals (2 times)