Specifications

Important

Unless otherwise stated, all specifications apply after 30 minutes of instrument warm-up.

Important

Important changes in the specification parameters are explicitly mentioned in the revision history of this document.

General Specifications

Table 1: General and storage

Parameter	Min	Typ	Max
storage temperature	–25 °C	-	65 °C
storage relative humidity (non-condensing)	-	-	95%
operating temperature	5 °C	-	40 °C
operating relative humidity (non-condensing)	-	-	90%
specification temperature	18 °C	-	28 °C
power consumption	-	-	300 W
operating environment	IEC61010, indoor location, installation category II, pollution degree 2
operating altitude	up to 2000 meters
power inlet fuses	250 V, 2 A, fast acting, 5 x 20 mm
power supply AC line	100-240 V (±10%), 50/60 Hz
dimensions (width x depth x height)	45.0 × 39.7 × 13.2 cm (no handle), 17.7 × 15.6 × 5.2 inch, 19 inch rack compatible
weight	15 kg (33 lb)
recommended calibration interval	2 years

Table 2: Maximum ratings

Parameter	Min	Typ	Max
damage threshold Signal Out	-10 V	-	+10 V
damage threshold Signal In	-3 V	-	+3 V
damage threshold Trig Out	–0.7 V	-	+4 V
damage threshold Ref/Trig In (1 kΩ input impedance)	–11 V	-	+11 V
damage threshold Ref/Trig In (50 Ω input impedance)	–6 V	-	+6 V
damage threshold Aux In (DC)	-10 V	-	+10 V
damage threshold Aux In (AC)	-3 V	-	+3 V
damage threshold External Clk In (DC)	–3 V	-	+3 V
damage threshold External Clk In (AC, with DC offset 0 V)	-1.5 V	-	+1.5 V
damage threshold External Clk Out (DC)	–3 V	-	+3 V
MDS In / Out	–0.7 V	-	+4 V
DIO In / Out in default configuration 3.3 V CMOS/TTL	–0.7 V	-	+4 V
torque limit front panel SMA connectors	-	-	0.5 Nm
torque limit back panel SMA connectors	-	-	1.0 Nm

Table 3: Host computer requirements

Parameter	Description
supported Windows operating systems	Windows 10, 8.1, 7 on x86-64
supported macOS operating systems	macOS 10.11+ on x86-64 and ARMv8
supported Linux distributions	GNU/Linux (Ubuntu 14.04+, CentOS 7+, Debian 8+) on x86-64 and ARMv8
minimum host computer requirements a	Windows 7 64-bit Dual Core CPU 4 GB DRAM 1 Gbit/s Ethernet controller
recommended host computer requirements a	Windows 10 or GNU/Linux or macOS Quad Core CPU (i7) or better 8 GB DRAM or better 1 Gbit/s Ethernet controller USB 3.0 connection
supported processors	x86-64 (Intel, AMD), ARMv8 (e.g., Raspberry Pi 4, Apple M1)

Analog Interface Specifications

Table 4: Signal Outputs

Parameter	Details		Min	Typ	Max
connectors	-		SMA, front panel single-ended
impedance	-		-	50 Ω	-
coupling	Baseband		AC/DC
	RF		AC
D/A converter vertical resolution	-		14 bit
D/A converter sampling rate	after internal x3 interpolation		6 GSa/s
measurement band	RF (measurement band around carrier, same for all carriers)		±500 MHz
	Baseband		800 MHz
total frequency range			DC	-	8.5 GHz
power range (into 50Ω)	Baseband		-30 dBm	-	+5 dBm
	RF		-30 dBm	-	+10 dBm
amplitude range (into 50Ω)	Baseband		10 mVpk	-	0.5 Vpk
	RF		10 mVpk	-	1 Vpk
level accuracy	into 50 Ω		-	±(1 dBm of setting)	-
frequency resolution	-		7 µHz
phase noise	100 MHz (Baseband)	offset 0.1 kHz	-	-141 dBc/Hz	-
		offset 1 kHz	-	-156.1 dBc/Hz	-
	1 GHz (RF)	offset 0.1 kHz	-	-102 dBc/Hz	-
		offset 1 kHz	-	-111 dBc/Hz	-
		offset 10 kHz	-	-114 dBc/Hz	-
		offset 100 kHz	-	-117 dBc/Hz	-
	4 GHz (RF)	offset 0.1 kHz	-	-99 dBc/Hz	-
		offset 1 kHz	-	-108 dBc/Hz	-
		offset 10 kHz	-	-114 dBc/Hz	-
		offset 100 kHz	-	-117 dBc/Hz	-
	6 GHz (RF)	offset 0.1 kHz	-	-101 dBc/Hz	-
		offset 1 kHz	-	-111 dBc/Hz	-
		offset 10 kHz	-	-112 dBc/Hz	-
		offset 100 kHz	-	-115 dBc/Hz	-
	8 GHz (RF)	offset 0.1 kHz	-	-97 dBc/Hz	-
		offset 1 kHz	-	-107 dBc/Hz	-
		offset 10 kHz	-	-111 dBc/Hz	-
		offset 100 kHz	-	-113 dBc/Hz	-
voltage spectral noise density	0 dBm, 1 GHz (Baseband)	offset > 200 kHz, into 50 Ω	-	10.3 nV/√Hz	-
	10 dBm,1 GHz (RF)		-	40 nV/√Hz	-
	10 dBm, 4 GHz (RF)		-	23 nV/√Hz	-
	10 dBm, 6 GHz (RF)		-	14 nV/√Hz	-
	10 dBm, 8 GHz (RF)		-	14 nV/√Hz	-
spurious free dynamic range (RF, excluding harmonics)	full frequency range	wide band measurement	47 dBc	-	-

Table 5: Signal Inputs

Parameter	Details		Min	Typ	Max
connectors	-		SMA, front panel single-ended
impedance	-		-	50 Ω	-
coupling	Baseband		AC/DC
	RF		AC
A/D converter vertical resolution	-		14 bit
A/D converter sampling rate	before internal x2 decimation		4 GSa/s
measurement band	RF (measurement band around carrier, same for all carriers)		±500 MHz
	Baseband		800 MHz
total frequency range			DC	-	8.5 GHz
power range (50Ω)	Baseband		-30 dBm	-	+10 dBm
	RF		-50 dBm	-	+10 dBm
amplitude range (50Ω)	Baseband		10 mVpk	-	1 Vpk
	RF		1 mVpk	-	1 Vpk
offset amplitude	Baseband		-	5%	-
voltage spectral noise density	200 kHz < f ≤800 MHz (Baseband)	10 mV range, 50 Ω	-	-	3.5 nV/√Hz
	>1 GHz (RF)	10 mV range, 50 Ω	-	-	2.5 nV/√Hz
spurious free dynamic range (excluding harmonics)	10 dBm	signal at center frequency, max. amplitude, -500 to 500 MHz	-	52 dBc	-
	0 dBm		-	52 dBc	-
	-10 dBm		-	52 dBc	-
	-20 dBm		-	47 dBc	-
	-30 dBm		-	52 dBc	-
	-40 dBm		-	52 dBc	-
	-45 dBm		-	47 dBc	-
	-50 dBm		-	42 dBc	-
3rd order intermodulation distortion	10 dBm	dual tone with -7 dBFS of range with 150 MHz Splitting from 1 GHz to 8 GHz	-	45 dBc	-
	0 dBm		-	54 dBc	-
	-10 dBm		-	54 dBc	-
	-20 dBm		-	56 dBc	-
	-30 dBm		-	54 dBc	-
	-40 dBm		-	50 dBc	-
	-50 dBm		-	40 dBc	-

Table 6: Demodulators

Parameter	Details	min	typ	max
number of demodulators	-	8
demodulator harmonic setting range	-	1	-	1023
demodulator filter time constant	-	14 ns	-	21 s
demodulator measurement bandwidth	-	3.2 mHz	-	11 MHz (with filter bypass)
demodulator filter slope/roll-off	-	6, 12, 18, 24 dB/oct, consisting of 4 cascaded filters

Table 7: Auxiliary outputs and inputs

Parameter	Details	min	typ	max
high-speed auxiliary output	connectors	BNC, 4 outputs on front panel
		sampling	50 MSa/s, 14 bit
		bandwidth (3 dB)	15 MHz
		impedance	50 Ω
		amplitude (into 50 Ω)	-4 V	-	+4 V
high-precision auxiliary output	connectors	BNC, 4 outputs on front panel
		sampling	1 MSa/s, 18 bit
		bandwidth (3 dB)	200 kHz
		impedance	50 Ω
		amplitude (into 50 Ω)	-4 V	-	+4 V

Table 8: Trigger Outputs & Inputs

Parameter	Details	Min	Typ	Max
trigger outputs	-	2 per channel, SMA output on front panel
trigger output high voltage	-	-	3.3 V	-
trigger output low voltage	-	-	0 V	-
trigger output impedance	-	-	50 Ω	-
trigger output rise time 20% to 80%	-	-	300 ps	-
trigger output period jitter	square wave, 100 MHz	-	60 ps p-p	-
trigger inputs	-	2 per channel, 2 SMA on front panel
trigger input impedance	-	50 Ω / 1 kΩ
trigger input voltage range	50 Ω impedance	–5 V	-	5 V
		1 kΩ impedance	–10 V	-	10 V
trigger input threshold range	50 Ω impedance	–5 V	-	5 V
		1 kΩ impedance	–10 V	-	10 V
trigger input threshold resolution	-	-	< 0.4 mV	-
trigger input threshold hysteresis	-	-	> 60 mV	-
trigger input min. pulse width	-	-	5 ns	-
trigger input max. operating frequency	-	-	300 MHz	-

Table 9: Other Inputs and Outputs

Parameter	Details	min	Typ	Max
reference clock input	-	SMA on back panel
reference clock input impedance	-	50 Ω, AC coupled
reference clock input frequency	-	10 / 100 MHz
reference clock input amplitude	10 MHz	-4 dBm	-	+13 dBm
		100 MHz	–5 dBm	-	+13 dBm
reference clock output	-	SMA on back panel
reference clock output impedance		50 Ω, AC coupled
reference clock output amplitude	into 50 Ω	2 Vpp	-	5 Vpp
reference clock output frequency		10/100 MHz
reference clock output jitter	derived from integrated phase noise measurement (12 kHz to 20 MHz offset frequency)	-	280 fs RMS	-

Table 10: Oscillator and Clocks

Parameter	Details	Min	Typ	Max
internal clock type	-	OCXO
internal clock long term accuracy / aging	-	-	-	±0.3 ppm/year
internal clock short term stability (1 s)	-	-	-	±0.05 ppm
internal clock initial accuracy	-	-	-	±0.5 ppm
internal clock temperature stability	–20°C to 70°C	-	-	±0.5 ppm
internal clock phase noise	offset 100 Hz	-	–135 dBc/Hz	-
		offset 1 kHz	-	–157 dBc/Hz	-

Digital Interface Specifications

Table 11: Digital Interfaces

Parameter	Description
host computer connection	USB 3.0, 1.6 Gbit/s (1 communication, 1 maintenance)
		1GbE, LAN / Ethernet, 1 Gbit/s
DIO port	4 x 8 bit, general purpose digital input/output port, 3.3 V TTL specification
ZSync peripheral port	connector for ZI proprietary bus to communicate with external peripherals (2 times)

DIO Port

The DIO port is a VHDCI 68 pin connector as introduced by the SPI-3 document of the SCSI-3 specification. It is a female connector that requires a 32 mm wide male connector. The interface standard is switchable between LVDS (low-voltage differential signalling) and LVCMOS/LVTTL. The DIO port features 32 user-controlled bits that can all be configured byte-wise as inputs or outputs in LVCMOS/LVTTL mode, whereas in LVDS mode, half of the bits are always configured as inputs. For more specifics on how the user-definable pins can be set.

Figure 1: DIO HD 68 pin connector

Table 12: Electrical Specifications

Parameter	Details	Min	Typ	Max
supported DIO interface standards	-	LVCMOS/LVTTL (single-ended, 3.3 V); LVDS (differential)
high-level input voltage VIH	LVCMOS/LVTTL	2.0 V	-	-
low-level input voltage VIL	LVCMOS/LVTTL	-	-	0.8 V
high-level output voltage VOH	LVCMOS/LVTTL at IOH < 12 mA	2.6 V	-	-
low-level output voltage VOL	LVCMOS/LVTTL at IOL < 12 mA	-	-	0.4 V
high-level output current IOH (sourcing)	LVCMOS/LVTTL	-	-	12 mA
low-level output current IOL (sinking)	LVCMOS/LVTTL	-	-	12 mA
input differential voltage VID	LVDS	100 mV	-	600 mV
input common-mode voltage VICM	LVDS	0.3 V	-	2.35 V
output differential voltage VOD	LVDS	247 mV	-	454 mV
output common-mode voltage VOCM	LVDS	1.125 V	-	1.375 V

Table 13: DIO Pin Assignment in LVCMOS/LVTTL Mode

Pin	Name	Description
68	CLKI	digital input
67	unused	leave unconnected
66 .. 59	DIO[31:24]	digital input or output byte (set by user)
58 .. 51	DIO[23:16]	digital input or output byte (set by user)
50 .. 43	DIO[15:8]	digital input or output byte (set by user)
42 .. 35	DIO[7:0]	digital input or output byte (set by user)
34	GND	digital ground
33	unused	leave unconnected
32 .. 1	GND	digital ground

Table 14: DIO Pin Assignment in LVDS Mode

Pin	Name	Description
68	CLKI+	digital input
67	unused	leave unconnected
66 .. 59	DI+[31:24]	digital input byte
58 .. 51	DI+[23:16]	digital input byte
50 .. 43	DIO+[15:8]	digital input or output byte (set by user)
42 .. 35	DIO+[7:0]	digital input or output byte (set by user)
34	CLKI–	digital input
33	unused	leave unconnected
32 .. 25	DI–[31:24]	digital input byte
24 .. 17	DI–[23:16]	digital input byte
16 .. 9	DIO–[15:8]	digital input or output byte (set by user)
8 .. 1	DIO–[7:0]	digital input or output byte (set by user)