The figure below shows the architecture of the DIO input/output. The DIO port features 32 bits that can be configured byte-wise as inputs or outputs by means of a drive signal. The digital output data is latched synchronously with the falling edge of the internal clock, which is running at 50 MHz. The internal sampling clock is available at the DOL pin of the DIO connector. Digital input data can either be sampled by the internal clock or by an external clock provided through the CLKI pin. A decimated version of the input clock is used to sample the input data. The Decimation unit counts the clocks to decimation and then latches the input data. The default decimation is 5625000, corresponding to a digital input sampling rate of 1 sample per second.
The table below shows the mapping between DIO pins and input/output signals available when using the DIO connector to output qubit state measurement results. The direction is as seen from the SHFSG instrument. In order to use these signals, the Digital I/O Mode and Drive setting have to be chosen accordingly.
Figure 2 belows shows an example of multiple channel readout transmissions through DIO. Every readout is sent in a single message. A one-hot encoding of the readout channel is sent along with the readout on dedicated bits. The valid bit is set for every valid DIO transaction.
The ZSync link of the Zurich Instruments' Quantum Computing Control System (QCCS) enables instrument synchronization and communication on the system level. With the PQSC Programmable Quantum System Controller as the central controller, the different instruments for qubit control and readout interface in a scalable architecture.
In particular, the ZSync links distribute the system clock to all instruments and synchronize all instruments to sub-nanosecond levels. Besides status monitoring to ensure quality and reliability of qubit tune-up routines, it provides a bidirectional data interface to send readout results to, or obtain sequence instructions from the PQSC.
The ZSync links adhere to strict real-time behavior: all data transfers are predictable to single-clock-cycle precision. In the SHFSG, the link is optimized for maximum data transfer to the central controller. For example, twice the bandwidth is reserved for results being transfered to the PQSC with respect to the allocated bandwith for instructions that are received from the PQSC. This enables global feedback and error correction through centralized syndrome decoding and synchronized actions on the global QCCS system level.
More information on the ZSync, and how to properly link the SHFSG with the QCCS can be found in the user manual of the PQSC Programmable Quantum System Controller.
When combined with an SHFQA for qubit readout and the PQSC for relaying and processing of the readout results, the SHFSG can help perform feedback and error correction protocols.
- command, the SHFQA generates a readout result and forwards it to the PQSC over the ZSync. Depending on the address provided, the PQSC stores it in the register bank - the center of the feedback in the QCCS system. After processing, the PQSC then forwards the results to other devices in the QCCS, such as the SHFSG.
The register bank requires a readout to have an address and a mask along with the readout data. Each component is sent in a separate ZSync message. The address is sent first, followed by the mask, and then the data, see Figure 3. To reduce latency, the address and the mask are sent during the readout, and the data is then sent as soon as the discriminated qubit results are ready.