DIO Tab

The DIO tab provides access to the settings and controls of the digital input and output. It is available on all SHFQA Instruments.

Features

  • Monitor and control of 32-bit DIO port

  • Communicate qubit states via 32-bit DIO port

  • Configure Trigger Input and Marker Output

Description

The DIO tab is the main panel to control the digital inputs and outputs as well as the trigger levels. Whenever the tab is closed or an additional one of the same type is needed, clicking the following icon will open a new instance of the tab.

Table 1. App icon and short description
Control/Tool Option/Range Description

DIO

btn mnu dio um

Gives access to all controls relevant for the digital inputs and outputs including DIO, Trigger Inputs and Marker Outputs.

shfqa dio tab
Figure 1. LabOne UI: DIO tab

The DIO tab includes 3 sub-tabs: Digital I/O for the 32-bit DIO port configuration, Trigger for the Trigger Input configuration, Marker for the Marker Output configuration. Table 3 provides all configurations of the 3 sub-tabs. The 32-bit Digital I/O, Trigger Input and Marker Output are often used in experiment sequences, see examples in Readout Pulse Generator Tab.

Digital I/O Sub-Tab

The Digital I/O sub-tab has 3 operation modes: Manual means controlled manually, QA Sequencer n means controlled by QA Sequencer n, QA there are the 32-bit DIO port is in use.

Figure 2 shows the architecture of the DIO port. It features 32 bits that can be configured byte-wise as inputs or outputs by means of a drive signal. The digital output data is latched synchronously with the falling edge of the internal clock, which is running at 50 MHz. The internal sampling clock is available at the DOL pin of the DIO connector. Digital input data can either be sampled by the internal clock or by an external clock provided through the CLKI pin. A decimated version of the input clock is used to sample the input data. The Decimation unit counts the clocks to decimation and then latches the input data. The default decimation is 5625000, corresponding to a digital input sampling rate of 1 sample per second.

uhf dio architecture
Figure 2. DIO input/output architecture

In Manual mode, each DIO pin can be controlled manually according to Figure 2 and the DIO interface specification is detailed in Specifications.

In QA Sequencer N mode, each DIO pin output can be controlled in the SHFQA Readout Pulse Generator Tab Sequencer N (N indicates which Channel) by a SeqC command setDIO.

In QA Results QCCS mode, DIO pins are configured to send Readout Result after Thresholding. Table 2 shows the mapping between DIO pins and input/output signals available when using the DIO connector to output qubit state measurement results. The direction is as seen from the SHFQA Instrument. In order to use these signals, the Digital I/O Mode and Drive setting have to be chosen accordingly.

Table 2. DIO signal assignment in QA Results QCCS mode
DIOLink signal DIO pin Direction Description

VALID

DIO[0]

OUT

valid bit

CW

DIO[4:1]

OUT

one-hot encoding of the SHFQA Channel

CW

DIO[8:23]

OUT

quantized results for up to 16 qubits

reserved

DIO[24:31]

IN

incoming communication

Figure 3 shows an example of multiple channel readout transmissions through DIO. Every readout is sent in a single message. A one-hot encoding of the readout channel is sent along with the readout on dedicated bits. The valid bit is set for every valid DIO transaction.

shf dio
Figure 3. DIO Result communication

The QA Results QCCS mode of the DIO interface provides one way of communicating discriminated qubit states between 2 Instruments. For more than 2 Instruments, both qubit states and synchronization becomes essential. The following section explains how the ZSync interface works for both Instrument synchronization and feedback. Please note that ZSync settings are under the Device Tab.

ZSync Interface

The ZSync link of the Zurich Instruments' Quantum Computing Control System (QCCS) enables Instrument synchronization and communication on the system level through the Zurich Instruments' PQSC Programmable Quantum System Controller. This architecture is able to support quantum algorithms run in scalable quantum processors.

In particular, the ZSync links distribute the system clock to all Instruments and synchronize all Instruments to sub-nanosecond levels. Besides status monitoring to ensure quality and reliability of qubit tune-up routines, it provides a bidirectional data interface to send readout results to, or obtain sequence instructions from the PQSC.

The ZSync links adhere to strict real-time behavior: all data transfers are predictable to single clock cycle precision. In the SHFQA, the link is optimized for maximum data transfer bandwidth to the central controller. For example, twice the bandwidth is reserved for results being transfered to the PQSC with respect to the allocated bandwith for instructions that are received from the PQSC. This enables global feedback and error correction through centralized syndrome decoding and synchronized actions on the global QCCS system level.

Feedback through the PQSC

More information on ZSync, and how to properly link the SHFQA with the QCCS can be found in the user manual of the PQSC Programmable Quantum System Controller.

Using the startQA- command, the SHFQA generates a readout result and forwards it to the PQSC over ZSync. Depending on the address provided, the PQSC stores it in the register bank - the center of feedback in the QCCS. After processing, the PQSC then forwards the results to other devices in the QCCS, such as the SHFSG.

The register bank requires a readout to have an address and a mask along with the readout data. Each component is sent in a separate ZSync message. The address is sent first, followed by the mask, and then the data, see Figure 4. To reduce latency, the address and the mask are sent during the readout, and the data is then sent as soon as the discriminated qubit results are ready.

readout single
Figure 4. Readout Result communication via ZSync

For the SHFQA with multiple channels, the forwarding of the readout results is interleaved to reduce latency. For example, if all four readout channels perform a readout at the same time, the SHFQA transmits the results of two channels on a single lane of a dual-lane ZSync. On each lane, the SHFQA first sends the header and mask of the two readout channels during the readout. The data is then sent as soon as it is available.

readout shf

Functional Elements

Table 3. DIO tab
Control/Tool Option/Range Description

Trigger Sub-Tab

Trigger Level

-10 V to 10 V

Trigger voltage level at which the trigger input toggles between low and high.

50 Ω

50 Ω/1 kΩ

Trigger input impedance: When on, the trigger input impedance is 50 Ω, when off 1 kΩ.

Trigger Input Low Status

Indicates the current low level trigger state.

Off

A low state is not being triggered.

On

A low state is being triggered.

Trigger Input High Status

Indicates the current high level trigger state.

Off

A high state is not being triggered.

On

A high state is being triggered.

Marker Sub-Tab

Marker Source

Select the signal assigned to the Marker Output.

Channel N, Sequencer Trigger Output

Trigger output is assigned to Readout Pulse Generator Sequencer N controlled by Sequencer commands.

Channel N, Readout done

Trigger output is assigned to Readout done of Channel N

Software Trigger 1

Trigger output is assigned to Software Trigger 1. There is only 1 Software Trigger in the SHFQA.

Digital I/O Sub-Tab

DIO Mode

Select DIO mode

Manual

Enables manual control of the DIO output bits.

QA Sequencer N

Enables setting of DIO output values by Readout Pulse Generator Sequencer commands.

QA Results QCCS

Enables setting of DIO output values by QA results.

QA Result Overflow

In QA Results QCCS mode, an overflow can happen if readouts are triggered faster than the maximum possible data-rate of the DIO interface.

grey/yellow/red

Red: present overflow condition on the DIO interface during readout.
Yellow: indicates an overflow occurred in the past.

DIO Bits

label

Partitioning of the 32 bits of the DIO into 4 buses of 8 bits each. Each bus can be used as an input or output.

DIO Input

numeric value in either Hex or Binary format

Current digital values at the DIO input port.

DIO Output

numeric value in either hexadecimal or binary format

Digital output values. Enable drive to apply the signals to the output.

DIO Drive

ON / OFF

When on, the corresponding 8-bit bus is in output mode. When off, it is in input mode.

Format

Select DIO view format.

Hexadecimal

DIO view format is hexadecimal.

Binary

DIO view format is binary.

Interface

Selects the interface standard to use on the 32-bit DIO interface. This setting is persistent across device reboots.

LVCMOS

A single-ended, 3.3V CMOS interface is used.

LVDS

A differential, LVDS compatible interface is used.